The present application is based on Japanese priority application No.2000-30818 filed on Feb. 8, 2000, the entire contents of which are hereby incorporated by reference.
The present invention generally relates to semiconductor devices and more particularly to a high-speed semiconductor device having a low-resistance self-aligned gate electrode and a fabrication process thereof.
Compound semiconductor devices are semiconductor devices that use a compound semiconductor material such as GaAs for a channel region thereof. Thus, compound semiconductor devices have excellent high-frequency operational characteristics and are used extensively for high frequency or ultrahigh-frequency amplifiers in various electronic apparatuses including cellular phones in the form of MMIC (microwave monolithic integrated circuit), in which the compound semiconductor devices are integrated together with analog passive devices.
Generally, a compound semiconductor device for an MMIC uses a gate electrode of a refractory metal or a conductive compound such as silicide, and a pair of diffusion regions of n+-type are formed in a compound semiconductor substrate, on which the compound semiconductor device is constructed, in a self-alignment process such that the n+-type diffusion regions are formed at both lateral sides of the gate electrode. In such a self-alignment process, the n+-type diffusion regions are formed by an ion implantation process while using the gate electrode as a self-alignment mask. An example of such a compound semiconductor device is a MESFET.
In such a self-aligned MESFET, it is possible to avoid the problem of degradation of the Schottky contact right underneath the gate electrode, which may be caused at the time of the thermal annealing process conducted typically at the temperature of about 800xc2x0 C. for activating the impurity elements introduced by the foregoing ion implantation process, by using a refractory conductive compound such as WSi for the gate electrode.
In view of the fact that such refractive conductive compounds have a resistivity larger than the resistivity of Au or Al, which is used commonly for a gate electrode of an ordinary MESFET, the gate electrode of the MESFET for use in such high-speed or microwave applications is generally formed to have a dual-layer structure in which a low-resistance metal electrode of W or Au is provided on the gate electrode of the refractory conductive compound for maximizing the operational speed.
Further, such a MESFET for microwave applications includes an ohmic electrode having a structure of Au/Ni/AuGe on the n+-type diffusion regions, wherein it should be noted that the AuGe component in the ohmic electrode forms an alloy at the interface to the GaAs substrate, and hence the desired ohmic contact.
In the case of analog circuits for ultra high-frequency applications, particularly an analog circuit for use in the final stage amplifier of a cellular phone, it is advantageous to integrate the compound semiconductor device on a compound semiconductor substrate together with other passive devices such as capacitors or inductances in the form of MMIC. By doing so, it becomes possible to eliminate the use of long interconnection wires and associated problems of parasitic capacitance and inductance. Thus, the construction of MMIC is thought advantageous for high-performance high-speed semiconductor devices.
FIGS. 1A-1E show a conventional process of forming an MMIC including a self-aligned MESFET therein.
Referring to FIG. 1A, a buried p-type layer 11A is formed in a semi-insulating GaAs substrate 11 in correspondence to the device region in which a self-aligned MESFET is to be formed, and a channel layer 11B of n-type is formed on the buried p-type layer with an impurity concentration level adjusted such that the MESFET to be formed has a desired threshold characteristic.
In the step of FIG. 1A, a gate electrode 12A of WSi is formed on the channel layer 11B and a low-resistance gate electrode 12B of W is formed on the gate electrode 12A. The WSi gate electrode 12A and the W gate electrode 12B form together a single gate electrode structure 12.
Next, in the step of FIG. 1B, an ion implantation process of an n-type impurity element is conducted while using the gate electrode structure 12 as a mask, and there are formed diffusion regions 11C and 11D of n+-type in the p-type buried layer 11A at both lateral sides of the gate electrode structure 12 after conducting a thermal annealing process.
Next, in the step of FIG. 1C, ohmic electrodes 13A and 13B having the Au/Ni/AuGe structure are formed on the GaAs substrate 11 respectively in ohmic contact with the diffusion regions 11C and 11D, and a passivation film 14 and an interlayer insulation film 15 are deposited consecutively on the structure of FIG. 1C.
Next, in the step of FIG. 1D, a contact hole 15A is formed in the interlayer insulation film 15 so as to penetrate through the passivation layer 14 and expose the ohmic electrode 13B, and a interconnection pattern 16A is formed on the interlayer insulation film 15 in correspondence to the contact hole 15A and an interconnection pattern 16A is formed on the interlayer insulation film 15 in correspondence to the contact hole 15A in electric contact with the ohmic electrode 13B.
In the step of FIG. 1D, another interconnection pattern 16B is formed on the interlayer insulation film 15 simultaneously to the interconnection pattern 16A, and the interconnection patterns 16A and 16B are covered by a dielectric film 17 of SiN, and the like, in the step of FIG. 1E. Further, an interlayer insulation film 18 is deposited in the step of FIG. 1F on the structure of FIG. 1E. Further, an opening 18A is formed in the interlayer insulation film 18 in correspondence to the electrode pattern 16B, and an electrode pattern 19 is formed on the interlayer insulation film 17 in correspondence to the foregoing opening 18A. Thereby, the electrode pattern 19 forms, together with the electrode pattern 16B and the dielectric film 17, a monolithic capacitor integral with the self-aligned MESFET.
The MMIC of FIG. 1F, while having the advantageous feature of integrating active devices operable in the ultra high-frequency band with a cooperating passive element, has a drawback in that it requires two interlayer insulation films, the layers 15 and 18, and three interconnection pattern layers, the first interconnection pattern layer including the ohmic electrodes 13A and 13B, the second interconnection pattern layer including the interconnection patterns 16A and 16B, and the third interconnection layer including the electrode pattern 19, and the fabrication process becomes inevitably complicated.
Further, the MMIC of FIG. 1F further has a drawback in that the use of a T-shaped gate structure for the gate electrode structure 12 for reducing the gate length of the lower gate electrode 12A for further increase of the operational speed while simultaneously maintaining sufficient size for the upper low-resistance electrode 12B for avoiding unwanted increase of gate resistance, is difficult. When such a T-shaped gate structure is used in the self-alignment process for forming the diffusion regions 11C and lD, the upper low-resistance gate electrode 12B acts as a mask and the diffusion regions 11C and 11D are formed with offset from the channel region right underneath the gate electrode 12A. When such an offset is caused, there occurs the problem of increase of the source resistance and hence the problem of decrease of conductance of the MESFET.
In the MMIC of FIG. 1F, it should be noted that the electrode pattern 16B forming the lower electrode of the capacitor is formed on the interlayer insulation film 15, due to the circumstances that the semi-insulating GaAs substrate 11 in fact has a weak n-type conductivity. Thus, in the case the lower electrode 16B is formed directly on the GaAs substrate 11, there is a possibility that a leakage current is caused to flow through the substrate 11 when a high voltage applied to the capacitor. Further, there is a risk, in the case the lower electrode 16B is formed directly on the GaAs substrate 11, in that the Au or Ge atoms in the lower electrode 16B, which includes an AuGe alloy, may cause a diffusion into the GaAs substrate 11 and form a leakage current path.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide an microwave monolithic integrated circuit including therein active devices and passive elements on a common substrate monolithically wherein the operational speed of the active devices is increased and the fabrication process is simplified.
Another object of the present invention is to provide a semiconductor device, comprising:
a compound semiconductor substrate;
a Schottky gate electrode formed on a first region of said compound semiconductor substrate with a first width;
a low-resistance gate electrode formed on said Schottky gate electrode with a second, larger width, said low-resistance gate electrode forming, together with said Schottky gate electrode, a T-shaped gate electrode structure;
a pair of ohmic electrodes making an ohmic contact with a surface of said compound semiconductor substrate in said first region at respective sides of said T-shaped gate electrode structure;
a lower electrode pattern formed on a second region of said compound semiconductor substrate in direct contact with said surface of said compound semiconductor substrate, said lower electrode pattern having a composition substantially identical with a composition of said low-resistance gate electrode;
a dielectric film formed on said lower electrode pattern: and
an upper electrode pattern formed on said dielectric film.
According to the present invention, it becomes possible to form a diffusion region adjacent to the refractive Schottky electrode having a reduced width and forming a lower part of a T-shaped gate electrode in a self-aligned process. Further, it becomes possible to form a lower electrode of a capacitor concurrently to the low-resistance electrode forming an upper part of the T-shaped gate electrode. Thereby, it becomes possible to form the integral structure of the active device and the capacitor efficiently. Particularly, the present invention can effectively and successfully minimize the leakage current in spite of the construction of providing the capacitor lower electrode directly on the compound semiconductor substrate by forming the second region of the compound semiconductor substrate in the form of a high-resistance region containing a p-type impurity element, rather than using a deep impurity element as practiced in the conventional art. By forming the first region such that the first region contains the same p-type impurity element contained in the second region with substantially an identical concentration, it becomes possible to form the first and second regions simultaneously. In view of the fact that the present invention no longer uses deep impurity element as noted above, there arises no problem with regard to the operation of the semiconductor device even when a high-resistance region is formed in the first region. By forming a p-type well in the first region so as to include the channel region and such that the p-type region of the p-type well is located underneath the n-type channel layer, it becomes possible to suppress the short-channel effect of the semiconductor device efficiently.
It should be noted that, in the semiconductor device of the present invention summarized above, it is possible to form a compound having the composition of AsTi and acting as a diffusion barrier on the surface of the compound semiconductor substrate by forming the lower electrode contacting directly with the surface of the compound semiconductor substrate in the second region by a Ti layer in direct contact with the compound semiconductor substrate and a low resistance metal layer formed on such a Ti layer. As a result of formation of such a diffusion barrier, the problem of diffusion of Au or Ge contained in the AuGe alloy constituting the capacitor lower electrode into the compound semiconductor substrate is effectively eliminated. Further, the Ti layer improves adhesion of the capacitor lower electrode to the compound semiconductor substrate.
In a further aspect of the present invention summarized above, it becomes possible to form first and second diffusion regions of n-type in the compound semiconductor substrate in alignment with the Schottky gate electrode even in such a case the compound semiconductor device has a T-shaped gate electrode structure. Accordingly, the present invention can avoid the problem of increase of source resistance caused in conventional semiconductor devices having a T-shaped gate electrode when the diffusion regions are formed in a self-alignment process by using the T-shaped gate electrode as a self-alignment mask. Further, it becomes possible to simplify the fabrication process of the semiconductor device by forming the dielectric film as a part of a passivation film protecting the surface of the semiconductor device.
In a further aspect of the present invention summarized above, it becomes possible to form a desired interconnection pattern on the compound semiconductor substrate by a simple process, by extending the high-resistance region forming the second region in the compound semiconductor substrate along a desired interconnection pattern and forming the interconnection pattern on such an extending high-resistance region with a composition substantially identical with the composition of the lower electrode pattern of the capacitor.
Another object of the present invention is to provide a microwave integrated circuit, comprising:
a compound semiconductor substrate;
an active device formed in a first region of said compound semiconductor substrate;
a high-resistance part formed in a second, different region of said compound semiconductor substrate; and
an interconnection pattern extending on the compound semiconductor substrate along said high-resistance part,
said high-resistance part containing a p-type impurity element,
said interconnection pattern comprising a Ti layer in contact with a surface of said compound semiconductor substrate directly and a low-resistance metal layer formed on said Ti layer.
According to the present invention, a desired interconnection pattern can be formed easily on a compound semiconductor substrate, by forming a high-resistance region containing a p-type element in the compound semiconductor substrate along the desired interconnection pattern. Thereby, the problem of increased leakage current, caused as a result of carrier trapping, is effectively eliminated by forming the high-resistance region by introducing a p-type impurity element rather than using a deep impurity element. Thus, the present invention is suitable for a microwave monolithic integrated circuit in which high-speed active devices are integrated with passive devices and interconnection patterns on a compound semiconductor substrate. In the present invention, too, the adherence of the low-resistance metal layer to the compound semiconductor substrate is improved due to the existence of the intervening Ti layer. Further, the problem of diffusion of the metal elements in the low-resistance metal layer into the substrate is eliminated.
Another object of the present invention is to provide a method of fabricating a microwave monolithic integrated circuit, comprising the steps of:
forming first and second high-resistance regions on a compound semiconductor substrate substantially simultaneously, by conducting an ion implantation process into a first and second regions of said compound semiconductor substrate;
forming an active device on said first region; and
forming a capacitor on said second region.
According to the present invention, it is possible to suppress the short-channel effect by increasing the resistance of the first region on which the active device is formed, by conducting an ion implantation process of a p-type impurity element into the first region. As a result of suppressing of the short-channel effect, the present invention can successfully maximize the operational speed of the active device. Further, formation of the high-resistance region in the second region, on which the capacitor is to be formed, by the ion implantation process of the p-type impurity element is effective for minimizing the leakage current to the compound semiconductor substrate from the capacitor. Thereby, it becomes possible to form the first and second high-resistance regions substantially simultaneously by using the same impurity element in the first and second high-resistance regions. As the present invention uses no deep impurity element for the first and second high-resistance regions, there occurs no adversary effect on the operation of the active device.
By implementing the process of forming the active device and the capacitor in the present invention summarized above according to the steps of: forming a Schottky gate electrode of a refractory metal compound on the first region; introducing an impurity element of an n-type into the first region of the compound semiconductor substrate while using the Schottky gate electrode as a mask; covering the surface of the compound semiconductor substrate by a first resist mask such that the first resist mask exposes the Schottky gate electrode in the first region and such that the first resist mask includes a first opening exposing the surface of the compound semiconductor substrate in the second region; covering the first resist mask with a second resist mask having a second opening exposing the Schottky gate electrode and a third opening exposing the first opening; depositing a low-resistance metal layer on the second resist mask such that the low-resistance metal layer covers the Schottky gate electrode at the second opening and such that the low-resistance metal layer covers the surface of the compound semiconductor substrate exposed at the third opening; lifting off the low-resistance metal layer deposited on the second resist mask such that the low-resistance metal layer remains on the Schottky electrode as a low-resistance gate electrode and such that the low-resistance metal layer remains on the second region as the lower electrode of the capacitor, it becomes possible to form the diffusion regions adjacent to the Schottky gate electrode by a self-alignment process even in such a case the active layer has the T-shaped gate electrode structure. Associated with this, it becomes possible to reduce the source resistance of the active device. As the upper, low-resistance electrode of the T-shaped gate electrode structure and the lower electrode of the capacitor on the compound semiconductor substrate are formed simultaneously according to the foregoing process, the efficiency of production of the microwave monolithic integrated circuit is improved.
By conducting the step of depositing the low-resistance metal layer by the steps of depositing a Ti layer and depositing the low-resistance metal layer on the Ti layer, it becomes possible to form a compound having a composition AsTi at the interface between the capacitor lower electrode and the compound semiconductor substrate, wherein the compound AsTi thus formed functions as a diffusion barrier and the diffusion of Au or Ge from the AuGe alloy contained in the capacitor lower electrode into the compound semiconductor substrate is effectively blocked.
By using a resist having a large sensitivity at the bottom part and smaller sensitivity at the top part for the second resist mask, it is possible to form the low-resistance gate electrode pattern to have a trapezoidal shape suitable for a lift-off process, such that the low-resistance gate electrode has a large base and a small top, both for the T-shaped gate electrode structure and the capacitor lower electrode.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.